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Renesas Electronics /R7FA6M3AH /BUS /CS3WCR1

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Interpret as CS3WCR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (others)CSPWWAIT 0 (others)CSPRWAIT 0 (others)CSWWAIT0 (others)CSRWAIT

CSWWAIT=others, CSPWWAIT=others, CSPRWAIT=others, CSRWAIT=others

Description

CS3 Wait Control Register 1

Fields

CSPWWAIT

Page Write Cycle Wait SelectNOTE: The CSPWWAIT value is valid only when the PWENB bit in CSnMOD is set to 1.

0 (0x0): No wait is inserted.

0 (others): Wait with a length of CSPWWAIT clock cycle is inserted.
CSPRWAIT

Page Read Cycle Wait SelectNOTE: The CSPRWAIT value is valid only when the PRENB bit in CSnMOD is set to 1.

0 (0x0): No wait is inserted.

0 (others): Wait with a length of CSPRWAIT clock cycle is inserted.
CSWWAIT

Normal Write Cycle Wait Select

0 (0x00): No wait is inserted.

0 (others): Wait with a length of CSWWAIT clock cycle is inserted.
CSRWAIT

Normal Read Cycle Wait Select

0 (0x00): No wait is inserted.

0 (others): Wait with a length of CSRWAIT clock cycle is inserted.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data